1. Field of the Invention
The present invention relates to constant current source circuits that are used in integrated circuits and are produced by way of CMOS integrated circuit technologies.
The present application claims priority on Japanese Patent Application No. 2007-258529, the content of which is incorporated herein by reference.
2. Description of Related Art
It becomes difficult for engineers to determine lower limits for operation voltages of analog circuits due to demands for reducing operation voltages of LSI (Large Scale Integration) circuits used in electronic devices having reduced power consumptions.
This is greatly affected by the fact in which threshold voltages Vt for MOS (Metal Oxide Semiconductor) transistors will not be subjected to scaling relative to reductions of operation voltages.
For example, when the minimum output voltage of a constant current source is to be reduced, it is necessary to reduce the threshold voltage Vt of a MOS transistor in response to a reduction of the operation voltage.
However, there is a limit in reducing the threshold voltage Vt due to an increase of a leak current.
When low currents flow through MOS transistors each having a very large area so as to secure certain voltage margins by reducing voltages applied thereto, the manufacturing cost may be pushed up so as to cause demerits economically.
Various types of LSI circuits essentially incorporate constant current source circuits which have low current reductions in case of low voltages and which can stabilize currents in a relatively broad range of voltages.
Various types of constant current source circuits have been developed and disclosed in various documents such as Patent Document 1 and Patent Document 2.                Patent Document 1: Japanese Unexamined Patent Application Publication No. H04-160511        Patent Document 2: Japanese Unexamined Patent Application Publication No. 2000-330657        
As a first example of the circuitry (serving as a constant current source circuit), FIG. 13 shows a current mirror circuit, wherein a reference current 10 flows through an n-channel MOS transistor M100 subjected to diode connection in which the same potential is applied to the gate and drain, hence, VGS0=VDS0.
A MOS transistor M101 is used as the output of the constant current source circuit, wherein when the gate voltage VGS0 is identical to the drain voltage VDS0, the same operation condition is applied to both of the transistors M100 and M101. When they have the same dimensions regarding the factor L/W (where L designates the channel length, and W designates the channel width), an output current I1 becomes identical to the reference current I0 (see Patent Document 1).
When an output voltage VOUT becomes higher than the gate voltage VGS0, the effective channel length may decrease due to the channel length modifying effect of the transistor while the drain voltage of the transistor M101 increases, wherein the output current I1 increases relative to the reference current I0 so that I1>I0, whereby the same current does not flow through the transistors M100 and M101.
In contrast, when the output voltage VOUT becomes lower than the gate voltage VGS0, the output current I1 decreases so that I1<I0, wherein the same current does not flow through the transistors M100 and M101.
FIG. 14 shows an example of IDS-VDS characteristics of an n-channel MOS transistor (where IDS designates a drain-source current, and VDS designates a drain-source voltage), whereby an output resistance rOUT of the circuitry of FIG. 13 substantially matches a drain resistance rDS1 of the transistor M101 when the inverse of the slope of the drain current IDS in the saturation region is expressed as rDS=ΔVDS/ΔIDS (where rDS designates a drain resistance).
In order to suppress variations of the output current I1 dependent upon the output voltage VOUT, it is necessary to increase the output resistance rOUT, whereas the circuitry of FIG. 13 suffers from a problem in that the output resistance rOUT cannot be increased to be higher than the drain resistance rDS1.
In the case that I0=100 μA and rDS1=50 kΩ, for example, current variations of 20 μA occur responsive to voltage variations of 1 V; this causes relatively high current variations of 20%/V, resulting in an incapability of supplying a constant current at a high precision.
As a second example of the circuitry which is designed as the countermeasure to the circuitry of FIG. 13 by increasing the output resistance of a constant current source, FIG. 15 shows a cascode current mirror circuit constituted of transistors M100, M101, M102, and M103 (see Patent Document 2).
In the case of Patent Document 2, the gate potential of the transistor M101 is identical to the gate potential VGS0, while the gate potential of the transistor M103 is identical to the gate potential VGS0+VGS2 of the transistor M102.
In the saturation region of the transistor M103, the gate-source voltage VGS3 of the transistor M103 is identical to the gate-source voltage VGS2 of the transistor M102; hence, the drain potential of the transistor M101 becomes identical to the gate-source voltage VGS0 of the MOS transistor M100.
Since potential variations of the output terminal do not affect the drain voltage of the transistor M101, it is possible to increase the output resistance rOUT, thus stabilizing the output current.
By use of the drain resistance rDS3 and the mutual conductance gm3 of the transistor M103, gate-source voltage variations ΔVGS3 of the transistor M103 dependent upon output voltage variations ΔVOUT is expressed as follows:
      Δ    ⁢                  ⁢          V              GS        ⁢                                  ⁢        3              =            Δ      ⁢                          ⁢              V        OUT                    gm      ⁢                          ⁢              3        ·                  r                      DS            ⁢                                                  ⁢            3                              
In the case that gm3=1 ms and rDS3=50 kΩ, for example, the above equation can be rewritten as ΔVGS3=ΔVOUT/50. This indicates that potential variations of the output terminal may affect the drain potential of the MOS transistor M100 by 1/50 of the actual variations.
The output resistance rOUT of the circuitry of FIG. 15 is expressed as follows:rOUT=(gm3·rDS3)·rDS1 
Compared with the circuitry of FIG. 13, the circuitry of FIG. 15 provides (gm3·rDS3) times higher output resistance. In the case that I0=100 μA, rDS1=rDS3=50 kΩ, and gm3=1 mS, for example, the above equation produces rOUT=2.5 MΩ, wherein potential variations of 1 V may result in current variations of 0.4 μA; hence, output current variations can be suppressed as 0.4%/V.
However, the present inventor has recognized that, in the constant current source circuit disclosed in Patent Document 2, due to the relatively high gate potential VGS0+VGS2 of the transistor M103, the transistor M103 produces the minimum value of the output voltage, i.e. VOUT(min), during the operation in the saturation region.VOUT(min)≧VGS0+VGS2−VT3 
This reduces the range of operation voltage of the transistor M103 by VGS2.
To cope with such a problem, as a further example of the constant current source circuit (having intermediate characteristics between the characteristics of Patent Document 1 and the characteristics of Patent Document 2), FIG. 16 shows a cascode current mirror circuit for use at a low voltage.
In the circuitry of FIG. 16 constituted of the four transistors M100 to M103, each of the drain voltages of the transistors M100 and M101 is expressed as VDS0=Vncas−VGS2 or VDS1=Vncas−VGS3 (where Vncas is a gate potential).
In the above, the drain voltages VDS0 and VDS1 are reduced by adjusting the gate potential Vncas with respect to the transistors M102 and M103, thus decreasing the lower limit of the operation voltage in a similar manner to the circuitry of FIG. 15.
Since both the drain voltages VDS0 and VDS1 are relatively low, both transistors M100 and M101 do not operate in the saturation region but in the linear region, wherein the characteristics thereof may be similar to resistance characteristics.
Since the drain voltages of the transistors M100 and M101 are maintained constant by way of the transistors M102 and M103, the circuitry of FIG. 16 is capable of operating as the constant current source.
The output resistance rOUT of the circuitry of FIG. 16 is identical to that of the circuitry of FIG. 15, where rOUT=(gm3·rDS3)·rDS1.
Compared with the circuitry of FIG. 15, the drain resistance rDS1 has a lower value in the circuitry of FIG. 16 that operates in the linear region. In the case that the current of 100 μA in which the gate potential Vncas is adjusted to achieve VDS1=200 mV, it is possible to calculate the drain resistance rDS1 by the following equation based on the approximation that the transistor M101 has a linear resistance.
      r          DS      ⁢                          ⁢      1        =                    200        ⁢                                  ⁢        mV                    100        ⁢                                  ⁢        µA              =          2      ⁢                          ⁢      k      ⁢                          ⁢      Ω      
In the case that rDS3=50 kΩ and gm3=1 mS (in a similar manner to the circuitry of FIG. 15), rOUT=100 kΩ, wherein current variations of 10 μA occur responsive to potential variations of 1 V; hence, it is possible to suppress output current variations by 10%/V.
The aforementioned calculations indicate that when the gate potential Vncas is intentionally reduced with respect to the transistors M102 and M103 in order to increase the lower-limit range of the operation voltage, the drain voltage VDS1 becomes low so that the drain resistance rDS1 correspondingly becomes low, thus reducing the output resistance rOUT.
In order to obtain the cascode effect in the aforementioned circuitries, it is necessary to establish a balance between the operation voltage and the output resistance by increasing the drain voltage VDS1.
In the case of the low-voltage cascode configuration, engineers cannot neglect a problem in that the range of the operation voltage is inevitably reduced by VDS1.